|SCIENTIFIC DISCIPLINARY SECTOR||ING-INF/01|
|MODULES||This unit is a module of:|
The course aims to provide expertise and to develop design skills on the following topics: architectures of integrated electronic systems, specification methodology, system description and automatic synthesis, top-down design flow, verification and simulation methodology, hardware description languages and test methodology.
Attendance and active participation in the proposed training activities (lectures and laboratories) and individual study will allow the student to:
- achieve an in-depth knowledge of the semantics of Hardware Description Languages (HDL), in particular of the VHDL language, and the syntax of VHDL that allows you to describe a digital electronic system at Register Transfer Level (RTL);
- learn the design methodology of a dedicated digital system (FPGA or ASIC standard cell) based on the use of HDL;
- know the main methodologies / technologies for the implementation of dedicated digital electronic systems i.e. field-programmable gate arrays (FPGAs), application-specific integrated circuit (ASIC);
- be able to analyze the design of a digital electronic system described in VHDL;
- be able to analyze and develop a dedicated digital electronic system based on an architecture: control system (Finite State Machine, FSM) + data processing system (data path)
- design a dedicated digital electronic system with FPGA or ASIC standard cell technologies/methodologies starting from the customer/user specifications in natural language.
The course is organized with lectures, for a total of about 40 hours, and with laboratory exercises of about 16 hours. Attendance to lectures and laboratories is compulsory, as per the didactic regulations. The laboratories will be held by the lecturer, assisted by laboratory tutor. A brief theoretical introduction is provided at the beginning of each laboratory activity with the aim of providing the basic principles on which the methodologies of description and synthesis of digital circuits on FPGA that will be used are based. In the practical part, the students, divided into groups of two or three members and with the support of the lecture and tutor, will have to apply the methodologies for the description / synthesis of digital circuits. The organization and the schedule of the laboratories will be communicated directly by the lecturer at the beginning of the course.
The course program includes the following topics:
The teaching material is published on the Aulaweb course page.
Reference textbooks are:
Other textbooks of interest:
Office hours: By appointment
MAURIZIO VALLE (President)
DANIELE CAVIGLIA (President Substitute)
All class schedules are posted on the EasyAcademy portal.
The exam consists of a written test and an oral test.
The written test includes three exercises related to the description of digital circuits in VHDL, to the synthesis of digital circuits, to the analysis of the timing of synchronous digital circuits. The maximum mark from the written test is 20 points. To access the oral exam, students must have passed the written exam with a minimum score of 12 points.
The oral exam focuses on the knowledge of the theoretical / practical topics taught during the course. The maximum score is 10 points.
The overall evaluation is given by the sum of the evaluation of the written and oral tests.
Three sessions will be available in the summer session and three sessions in the winter session.
Students with learning disorders ("disturbi specifici di apprendimento", DSA) will be allowed to use specific modalities and supports that will be determined on a case-by-case basis in agreement with the delegate of the Engineering courses in the Committee for the Inclusion of Students with Disabilities.
More details on how to prepare for the exam and the degree of depth of each topic will be given during the lectures. The written test will verify the actual acquisition of knowledge relating to the analysis and synthesis of dedicated digital circuits using the VHDL language at the RTL level as a support tool.
The oral exam will mainly focus on the topics covered during the lectures and laboratories and will aim to assess not only if the student has reached an adequate level of knowledge, but if he has acquired the ability to critically analyze the project methodologies of dedicated digital systems / circuits. Furthermore, the student's ability to effectively and accurately use the VHDL language to describe digital circuits will be assessed.
|13/01/2023||09:00||GENOVA||Scritto||Aula G2A - appuntamento alle ore 09.15|
|09/02/2023||09:00||GENOVA||Scritto||Aula G2A - appuntamento alle ore 09.15|
|16/06/2023||09:00||GENOVA||Scritto||Aula G2A - appuntamento alle ore 09.15|
|11/07/2023||09:00||GENOVA||Scritto||Aula G2A - appuntamento alle ore 09.15|
|12/09/2023||09:00||GENOVA||Scritto||Aula G2A - appuntamento alle ore 09.15|