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CODE 106773
ACADEMIC YEAR 2023/2024
CREDITS
SCIENTIFIC DISCIPLINARY SECTOR ING-INF/01
LANGUAGE Italian (English on demand)
TEACHING LOCATION
  • GENOVA
SEMESTER 1° Semester
MODULES Questo insegnamento è un modulo di:
TEACHING MATERIALS AULAWEB

AIMS AND CONTENT

LEARNING OUTCOMES

The course aims to provide expertise and to develop design skills on the following topics: architectures of integrated electronic systems, specification methodology, system description and automatic synthesis, top-down design flow, verification and simulation methodology, hardware description languages and test methodology.

AIMS AND LEARNING OUTCOMES

The course aims to provide expertise and to develop design skills on the following topics: architectures of integrated electronic systems, specification methodology, system description and automatic synthesis, top-down design flow, verification and simulation methodology, hardware description languages and test methodology.

Attendance and active participation in the proposed training activities (lectures and laboratories) and individual study will allow the student to:

- achieve an in-depth knowledge of the semantics of Hardware Description Languages (HDL), in particular of the VHDL language, and the syntax of VHDL that allows you to describe a digital electronic system at Register Transfer Level (RTL);

- learn the design methodology of a dedicated digital system (FPGA or ASIC standard cell) based on the use of HDL;

- know the main methodologies / technologies for the implementation of dedicated digital electronic systems i.e. field-programmable gate arrays (FPGAs), application-specific integrated circuit (ASIC);

- be able to analyze the design of a digital electronic system described in VHDL;

- be able to analyze and develop a dedicated digital electronic system based on an architecture: control system (Finite State Machine, FSM) + data processing system (data path)

- design a dedicated digital electronic system with FPGA or ASIC standard cell technologies/methodologies starting from the customer/user specifications in natural language.

TEACHING METHODS

The course is organized with lectures, for a total of about 40 hours, and with laboratory exercises of about 16 hours. Attendance to lectures and laboratories is compulsory, as per the didactic regulations. The laboratories will be held by the lecturer, assisted by laboratory tutor. A brief theoretical introduction is provided at the beginning of each laboratory activity with the aim of providing the basic principles on which the methodologies of description and synthesis of digital circuits on FPGA that will be used are based. In the practical part, the students, divided into groups of two or three members and with the support of the lecture and tutor, will have to apply the methodologies for the description / synthesis of digital circuits. The organization and the schedule of the laboratories will be communicated directly by the lecturer at the beginning of the course.

SYLLABUS/CONTENT

The course program includes the following topics:

  • Introduction to the description of a digital electronic system at Register Transfer Level
  • Circuit implementation of Flip-Flop and Latches
  • Power / energy consumption model of digital circuits in CMOS technology
  • Analysis of timing and response times
  • Metastability and related issues
  • Organization of data flow and pipeline processing
  • Design methodologies and management aspects e.g. recurring and non-recurring costs
  • Standard cell ASIC and FPGA methodologies and technologies
  • Introduction to Hardware Description Language (HDL)
  • Basic constructs and instructions
  • Concurrent assignment Instructions
  • Sequential assignment instructions
  • Circuit synthesis of VHDL code
  • Design of sequential digital circuits
  • Finite State Machine (FSM)
  • RTL-based Synthesis / Project Methodology
  • System structure and project: control and Data Paths (i.e. FSMD)

This course, dealing with topics of scientific-technological interest such as digital integrated electronic systems, contributes to the achievement of the following Sustainable Development Goals of the UN 2030 Agenda:

8.2 (Achieving higher standards of economic productivity through diversification, technological progress and innovation, also with particular attention to high added value and work intensive sectors)

9.5 (Increase scientific research, improve the technological capabilities of the industrial sector in all states - especially in developing countries - as well as encourage innovations and substantially increase, by 2030, the number of employees for every million people, in the research and development sector and expenditure on research – both public and private – and on development)

RECOMMENDED READING/BIBLIOGRAPHY

The teaching material is published on the Aulaweb course page.

Reference textbooks are:

  • Pong. P. Chu, RTL HardwareDesign Using VHDL, J. Wiley and Sons, 2006.
  • N.H.E. Weste, D.M. Harris, CMOS VLSI Design – A circuit and system perspective, 4th Ed., Addison Wesley Publisher, 2011
  • Jan M. Rabaey - Anantha Chandrakasan - Borivoje Nicolic, Circuiti integrati digitali 2/Ed., L'ottica del progettista, Pearson, ISBN9788871922317
  • M. Olivieri, Elementi di Progettazione dei Sistemi VLSI, EdiSes s.r.l., Napoli, 2004

Other textbooks of interest:

  • F. Vahid, Digital Design, J. Wiley and Sons, 2002
  • Douglas R. Perry, “VHDL: Programming by example”, 4th Ed., 2002,Mc Graw Hill, DOI: 10.1036/0071409548.
  • Pong. P. Chu, FPGA prototyping by VHDL examples, J. Wiley and Sons, 2008.
  • Mark Zwolinski, Digital System Design With VHDL, 2nd Edition, ISBN 0-13-039985-X

TEACHERS AND EXAM BOARD

Exam Board

MAURIZIO VALLE (President)

LUCA NOLI

LUCIA SEMINARA

ORAZIO AIELLO (President Substitute)

DANIELE CAVIGLIA (President Substitute)

LESSONS

Class schedule

The timetable for this course is available here: Portale EasyAcademy

EXAMS

EXAM DESCRIPTION

The exam consists of a written test and an oral test.

The written test includes three exercises related to the description of digital circuits in VHDL, to the synthesis of digital circuits, to the analysis of the timing of synchronous digital circuits. The maximum mark from the written test is 20 points. To access the oral exam, students must have passed the written exam with a minimum score of 12 points.

The oral exam focuses on the knowledge of the theoretical / practical topics taught during the course. The maximum score is 10 points.

The overall evaluation is given by the sum of the evaluation of the written and oral tests.

Three sessions will be available in the summer session and three sessions in the winter session.

Students with learning disorders ("disturbi specifici di apprendimento", DSA) will be allowed to use specific modalities and supports that will be determined on a case-by-case basis in agreement with the delegate of the Engineering courses in the Committee for the Inclusion of Students with Disabilities.

ASSESSMENT METHODS

More details on how to prepare for the exam and the degree of depth of each topic will be given during the lectures. The written test will verify the actual acquisition of knowledge relating to the analysis and synthesis of dedicated digital circuits using the VHDL language at the RTL level as a support tool.

The oral exam will mainly focus on the topics covered during the lectures and laboratories and will aim to assess not only if the student has reached an adequate level of knowledge, but if he has acquired the ability to critically analyze the project methodologies of dedicated digital systems / circuits. Furthermore, the student's ability to effectively and accurately use the VHDL language to describe digital circuits will be assessed.

Exam schedule

Data Ora Luogo Degree type Note
12/01/2024 09:30 GENOVA Scritto Aula D1
08/02/2024 09:30 GENOVA Scritto Aula D1
14/06/2024 09:30 GENOVA Scritto Aula D1
15/07/2024 09:30 GENOVA Scritto Aula D1
10/09/2024 09:30 GENOVA Scritto Aula D1

Agenda 2030 - Sustainable Development Goals

Agenda 2030 - Sustainable Development Goals
Quality education
Quality education
Gender equality
Gender equality
Industry, innovation and infrastructure
Industry, innovation and infrastructure