CODE 111454 ACADEMIC YEAR 2025/2026 CREDITS 6 cfu anno 1 INFORMATICA 11896 (L-31 R) - GENOVA SCIENTIFIC DISCIPLINARY SECTOR INF/01 LANGUAGE Italian TEACHING LOCATION GENOVA SEMESTER 2° Semester MODULES Questo insegnamento è un modulo di: COMPUTER ARCHITECTURE AND ORGANIZATION AIMS AND CONTENT LEARNING OUTCOMES Understanding the performance of sequential programs using the notions acquired regarding how current architectures works, i.e. the processor architecture, the memory hierarchies, and the cooperation between hardware and software. Understanding the architecture of GPUs, with reference to applicative areas and performance. AIMS AND LEARNING OUTCOMES The student will acquire the necessary skills to understand how high-level programmes are executed by modern computers. The choice of reference architecture is a key aspect. In continuation of the previous module, the RISC-V architecture has been chosen as it offers a simple, elegant, modern, open source model that is also of growing interest in the non-academic sphere. At the end of the course, the student will be able to: analyse the digital components that underpin the architecture of modern computers; describe how simple programs in RISC-V assembler are executed in this architecture; understand how a computer translates a high-level language into machine language; understand how program performance depends on the effective use of architectural features, such as efficient use of cache, vectorisation, and multi-threading programming; use a compiler more effectively by specifying certain flags for code optimisation. PREREQUISITES No specific prerequisites are required. TEACHING METHODS Lectures, classroom exercises, ongoing assignment with delivery and evaluation. Instant polling will be used for self-assessment and didactics for groups and cases/problems. SYLLABUS/CONTENT Sequential Circuits Flip-Flops, Latches, and Registers Moore's reference architecture for the synthesis of sequential circuits Memory Hierarchy Memory organization, temporal and spatial locality SRAM and DRAM memories Basic principles and performance of cache memories Modern Processors Pipelining and hazards in RISC-V architecture Word-level parallelism Instruction-level parallelism Vector processors Hardware multithreading Introduction to GPUs RECOMMENDED READING/BIBLIOGRAPHY David A Patterson John L Hennessy Struttura e progetto dei calcolatori Progettare con RISC-V Seconda edizione italiana ISBN: 9788808199669 TEACHERS AND EXAM BOARD DANIELE D'AGOSTINO Ricevimento: By appointment, in presence or via TEAMS. GIORGIO DELZANNO Ricevimento: Appointment by email LESSONS LESSONS START According to the calendar approved by the Degree Program Board: https://corsi.unige.it/corsi/11896/studenti-orario Class schedule The timetable for this course is available here: Portale EasyAcademy FURTHER INFORMATION For further information, please refer to the course’s AulaWeb module or contact the instructors.
