The student will acquire the necessary skills to understand how high-level programs are translated into the language of computers.
The choice of instruction set architecture is a key aspect. It was decided to adopt the RISC-V architecture as it offers a simple, elegant, modern, open source model of growing interest even in the non-academic field. At the end of the course the student will be able to: write and interpret simple RISC-V assembler programs; understand how a computer translates a high-level language into machine language; analyze program performance considering aspects such as efficient use of cache, vectorization, and multithreaded programming; use a compiler effectively.
Furthermore students will acquire basic skills on learning to learn, basic personal and social skills through didactics for groups, cases/problems
Lectures, classroom exercises, ongoing assignment with delivery and evaluation. Instant polling will be used for self-assessment and didactics for groups and cases/problems.
The RISC-V processor
RISC-V ISA Representation of instructions in the computer The main instructions Operands and addresses Translating and starting a program (assembler, linker, loader)
Memory hierarchy
Organization of memories, temporal and spatial locality Basic principles and performance of cache memories
Modern processors
Pipelining and hazards in Risc-V architecture Parallelism at the word level Instruction level parallelism Vector processors Hardware multithreading Introduction to GPUs
Students will acquire basic skills on: learning to learn, social and personal competence
David A Patterson John L HennessyStruttura e progetto dei calcolatoriProgettare con RISC-VSeconda edizione italianaISBN: 9788808199669
Chapters 2, 4 (4.5-4.10), 5 (5.6-5.10), 6 (6.1-6.6) Appendix C
Ricevimento: Appointment by email or via TEAMS.
Ricevimento: Appointment by email
DAVIDE ANCONA (President)
GIORGIO DELZANNO (President)
DANIELE D'AGOSTINO (President Substitute)
