AIMS AND CONTENT

LEARNING OUTCOMES

The module introduces notions and methodologies for the analysis and design of digital systems, covering the principal aspects from combinational and sequential logic to finite state machines, thus allowing for the design and simulation of simple digital systems containing standard logic and finite state machines.

AIMS AND LEARNING OUTCOMES

The course aims to teach students to specify, analyse, design and verify simple digital systems, from combinational logic to finite-state machines.

At the end of the course the student will be able to:

• represent information in binary and hexadecimal;
• analyse and minimise Boolean functions using canonical forms, Karnaugh maps and don't-care conditions;
• design combinational circuits with logic gates and standard blocks;
• draw timing diagrams of latches, flip-flops, and compute the maximum clock frequency of a synchronous circuit;

TEACHING METHODS

• Lectures with worked examples and in-class questions (approx. 80%, to develop the ability to learn to learn)
• Exercise sessions (approx. 20%, to develop personal competence)

Students who hold valid certificates relating to Specific Learning Difficulties (SLD), disabilities or other educational needs are invited to contact the lecturer and the school’s disability liaison officer at the start of the course to agree on any teaching arrangements which, whilst respecting the course objectives, take into account individual learning styles. 

The contact details for the university’s disability liaison officer are available at the following link: https://unige.it/commissioni/comitatoperlinclusionedeglistudenticondisabilita. 

SYLLABUS/CONTENT

1. Digital information and Boolean algebra: binary encoding, logic gates, Boolean identities, equivalence of expressions.
2. Canonical forms and minimisation: SOP and POS forms, don't-care conditions, Karnaugh maps.
3. Combinational design: from specification to verified circuit; decoders and multiplexers.
4. Binary arithmetic: unsigned and two's-complement numbers, adders, carry and overflow.
5. Memory elements: latches; D, JK and T flip-flops; timing diagrams.
6. Synchronous systems: registers, counters, setup and hold times, maximum clock frequency.
7. Finite-state machines: Moore and Mealy machines, state diagrams, state encoding, implementation with flip-flops.

RECOMMENDED READING/BIBLIOGRAPHY

• Donzellini, G., Oneto, L., Ponta, D., Anguita, D., Introduction to Digital Systems Design, Springer, 2019.
• Harris, S., Harris, D., Digital Design and Computer Architecture, RISC-V Edition, Elsevier, 2021.
• Donzellini, G., Oneto, L., Ponta, D., Anguita, D., Introduzione al Progetto di Sistemi Digitali, Springer, 2018.
• Fummi, F., Lora, M., Sami, M., Silvano, C., Progettazione digitale, 3rd ed., McGraw-Hill, 2023.

TEACHERS AND EXAM BOARD

Exam Board

FULVIO MASTROGIOVANNI (President)

LESSONS

LESSONS START

https://easyacademy.unige.it/portalestudenti/index.php?view=easycourse&_lang=it&include=corso

Class schedule

DIGITAL SYSTEMS DESIGN

EXAMS

EXAM DESCRIPTION

Written exam [1,5 hrs] with exercises covering the whole programme.

ASSESSMENT METHODS

The written exam assesses the ability to analyse and design combinational circuits, sequential circuits and finite-state machines, and to verify the results. Evaluation considers the correctness of the result and of the procedure, and the correct use of notation and terminology.

FURTHER INFORMATION

Students with valid certifications for Specific Learning Disorders (SLD) may request accommodations for exams at least 7 days prior to the exam date by filling out the “accommodation request form” (available via online services at https://modulionline.unige.it/richiesta-adattamenti# no-back), which will be automatically forwarded by the system to the instructor in charge of the course and to the faculty liaison for students with disabilities and SLDs in their School/Department. 

The student will receive a copy of their request.