AIMS AND CONTENT

LEARNING OUTCOMES

The module provides expertise and design skills on dedicated and integrated digital synchronous circuits and systems (e.g. FPGA and Application Specific Integrated Circuits) i.e. system architectures, circuit blocks, clock timing design, design flow and approaches, hardware description languages as support design tools.

AIMS AND LEARNING OUTCOMES

Attendance and active participation in the proposed learning activities (lectures and laboratory sessions), together with individual study, will enable students to:

• acquire a thorough understanding of Hardware Description Languages (HDLs), with particular emphasis on the semantics and syntax of VHDL for the description of digital electronic systems at the Register Transfer Level (RTL);
• understand and apply the design methodology of dedicated digital systems based on HDL descriptions, targeting both FPGA and ASIC standard-cell implementations;
• gain knowledge of the main technologies and methodologies used for the implementation of dedicated digital electronic systems, including Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs);
• analyze and evaluate the design of digital electronic systems described in VHDL;
• analyze, develop, and validate dedicated digital systems based on a control-and-datapath architecture, consisting of a Finite State Machine (FSM) and a data-processing unit;
• design dedicated digital electronic systems using FPGA or ASIC standard-cell technologies, starting from customer or user specifications expressed in natural language and translating them into efficient hardware implementations.

TEACHING METHODS

The course is organized with lectures, for a total of about 40 hours, and with laboratory exercises of about 16 hours. Attendance to lectures and laboratories is compulsory, as per the didactic regulations. The laboratories will be held by the lecturer, assisted by laboratory tutor. A brief theoretical introduction is provided at the beginning of each laboratory activity with the aim of providing the basic principles on which the methodologies of description and synthesis of digital circuits on FPGA that will be used are based. In the practical part, the students, divided into groups of two or three members and with the support of the lecture and tutor, will have to apply the methodologies for the description / synthesis of digital circuits. The organization and the schedule of the laboratories will be communicated directly by the lecturer at the beginning of the course.

SYLLABUS/CONTENT

The course program includes the following topics:

• Introduction to the description of a digital electronic system at Register Transfer Level
• Circuit implementation of Flip-Flop and Latches
• Power / energy consumption model of digital circuits in CMOS technology
• Analysis of timing and response times
• Metastability and related issues
• Organization of data flow and pipeline processing
• Design methodologies and management aspects e.g. recurring and non-recurring costs
• Standard cell ASIC and FPGA methodologies and technologies
• Introduction to Hardware Description Language (HDL)
• Basic constructs and instructions
• Concurrent assignment Instructions
• Sequential assignment instructions
• Circuit synthesis of VHDL code
• Design of sequential digital circuits
• Finite State Machine (FSM)
• RTL-based Synthesis / Project Methodology
• System structure and project: control and Data Paths (i.e. FSMD)

RECOMMENDED READING/BIBLIOGRAPHY

The teaching material is published on the Aulaweb course page.

Reference textbooks are:

• Pong. P. Chu, RTL HardwareDesign Using VHDL, J. Wiley and Sons, 2006.
• N.H.E. Weste, D.M. Harris, CMOS VLSI Design – A circuit and system perspective, 4th Ed., Addison Wesley Publisher, 2011
• Jan M. Rabaey - Anantha Chandrakasan - Borivoje Nicolic, Circuiti integrati digitali 2/Ed., L'ottica del progettista, Pearson, ISBN9788871922317
• M. Olivieri, Elementi di Progettazione dei Sistemi VLSI, EdiSes s.r.l., Napoli, 2004

Other textbooks of interest:

• F. Vahid, Digital Design, J. Wiley and Sons, 2002
• Douglas R. Perry, “VHDL: Programming by example”, 4th Ed., 2002,Mc Graw Hill, DOI: 10.1036/0071409548.
• Pong. P. Chu, FPGA prototyping by VHDL examples, J. Wiley and Sons, 2008.
• Mark Zwolinski, Digital System Design With VHDL, 2nd Edition, ISBN 0-13-039985-X

TEACHERS AND EXAM BOARD

LESSONS

Class schedule

The timetable for this course is available here: Portale EasyAcademy

EXAMS

EXAM DESCRIPTION

The examination consists of a written test followed by an oral examination.

The written test includes three exercises concerning the analysis, design, and description of digital systems using the VHDL hardware description language. The exercises may involve RTL modeling, synthesis of combinational and sequential circuits, timing analysis of synchronous digital systems, and interpretation of synthesis results.

The maximum score for the written test is 20 points. Students must obtain at least 12 points out of 20 to be admitted to the oral examination.

The oral examination consists of a discussion of the theoretical and practical topics covered during lectures and laboratory activities. Topics may include digital design methodologies, hardware description languages, synthesis techniques, timing verification, and implementation aspects of digital systems. The maximum score for the oral examination is 10 points.

The final grade is obtained by summing the scores achieved in the written and oral examinations.

ASSESSMENT METHODS

Detailed information regarding the examination content and the expected level of knowledge for each topic will be provided during the course.

The written test is designed to assess the student's ability to apply the concepts and methodologies presented during the course to the analysis and design of digital systems. In particular, it evaluates the student's capability to:

• develop correct RTL descriptions of digital circuits using VHDL;
• analyze the behavior of combinational and sequential digital systems;
• perform synthesis-oriented design activities;
• evaluate timing constraints and verify the correctness of synchronous digital circuits;
• interpret design results and justify design choices.

The oral examination aims to verify the student's understanding of the theoretical foundations of digital system design and the ability to critically discuss design methodologies and implementation solutions. Particular attention is devoted to the student's ability to:

• explain the principles underlying digital circuit design and hardware description languages;
• compare alternative design approaches and justify engineering choices;
• critically analyze architecture, performance, and implementation trade-offs;
• discuss the results obtained during design and synthesis activities;
• communicate technical concepts using appropriate terminology and a rigorous engineering approach.

The overall evaluation takes into account the correctness of the proposed solutions, the ability to apply theoretical knowledge to practical design problems, the level of autonomy in problem solving, the quality of the technical reasoning, and the use of appropriate scientific and technical language.